Computers have buses to transfer data between a host processor and various devices, such as memory devices and input/output devices. As used herein an “input/output” device is a device that either generates an input or receives an output (or does both). Thus “input/output” is used in the disjunctive. These buses may be arranged in a hierarchy with the host processor connected to a high level bus reserved for exchanging the data most urgently needed by the processor. Lower level buses may connect to devices having a lower priority.
Other reasons exist for providing separate buses. Placing an excessive number of devices on one bus produce high loading. Such loading makes a bus difficult to drive because of the power needed and the delays caused by signaling so many devices. Also, some devices on a bus may periodically act as a master and request control over a bus in order to communicate with a slave device. By segregating some devices on a separate bus, master devices can communicate with other devices on the lower level bus without tying up the bus used by the host processor or other masters.
The PCI bus standard is specified by the PCI Special Interest Group of Hillsboro, Oreg. The PCI bus features a 32-bit wide, multiplexed address-data (AD) bus portion, and can be expanded to a 64-bit wide AD bus portion. Maintaining a high data throughput rate (e.g., a 33 MHZ clock rate) on the PCI bus leads to a fixed limitation on the number of electrical AC and DC loads on the bus. Speed considerations also limit the physical length of the bus and the capacitance that can be placed on the bus by the loads, while future PCI bus rates (e.g., 66 MHZ and higher) will exacerbate the electrical load and capacitance concerns. Failure to observe these load restrictions can cause propagation delays and unsynchronized operation between bus devices.
To circumvent these loading restrictions, the PCI bus standard specifies a bridge to allow a primary PCI bus to communicate with a secondary PCI bus through such a bridge. Additional loads may be placed on the secondary bus without increasing the loading on the primary bus. For bridges of various types see U.S. Pat. Nos. 5,548,730 and 5,694,556.
The PCI bridge observes a hierarchy that allows an initiator or bus master on either bus to complete a transaction with a target on the other bus. As used herein, hierarchy refers to a system for which the concept of a higher or lower level has meaning. For example, a PCI bus system is hierarchical on several scores. An ordering of levels is observed in that a high-level host processor normally communicates from a higher level bus through a bridge to a lower level bus. An ordering of levels is also observed in that buses at equal levels do not communicate directly but through bridges interconnected by a higher level bus. Also, an ordering of levels is observed in that data is filtered by their addresses before being allowed to pass through a bridge, based on the levels involved. Other hierarchical systems exist that may observe an ordering of levels by using one or more of the foregoing concepts, or by using different concepts.
Some personal computers have slots for add-on cards, which allow the card to connect to a peripheral bus in the computer. Because a user often needs additional slots, expansion cards have been designed that will connect between the peripheral bus and an external unit that offers additional slots for add-on cards. For systems for expanding a bus, see U.S. Pat. Nos. 5,006,981; 5,191,657; and 5,335,329. See also U.S. Pat. No. 5,524,252.
For portable computers, special considerations arise when the user wishes to connect additional peripheral devices. Often a user will bring a portable computer to a desktop and connect through a docking station or port replicator to a keyboard, monitor, printer or the like. A user may also wish to connect to a network through a network interface card in the docking station. At times, a user may need additional devices such as hard drives or CD-ROM drives. While technically possible to a limited extent, extending a bus from a portable computer through a cable is difficult because of the large number of wires needed and because of latencies caused by a cable of any significant length.
In order for devices to function on a bus, valid ranges for I/O and various memory accesses must be supplied, these address assignments are referred to as resources. The devices on a PCI bus contain registers in configuration space that contain this resource information. The requirements to properly assign this information is defined and detailed by the specifications contained in the PCI local bus standards from 1.0 to 2.2 as specified by the PCI Special Interest Group of Hillsboro, Oreg.The process of locating these devices on a bus is referred to as enumeration. Of particular interest to bridges is the enumeration of the various hierarchical buses. The methods of enumeration when bridges are used may vary as long as the resulting configuration conforms to the PCI standards specification. In an effort to properly assign these resources a BIOS or operating system “OS” will test these assignments to determine if there are any conflicts or errors. In a properly designed system the resources are re-assigned correctly if an error occurs. These errors are especially prone to occur when multiple buses are employed due to the difficulties in analyzing all of the resources required by the devices at the various levels. When multiple buses are employed they are given numbers to identify them as unique buses. Obviously if a number is given to more then one bus then neither bus would be unique and conflicts can occur. The process of re-balancing is to reassign bus numbers to create a hierarchical bus number tree with all bus numbers being unique. The definitions of primary, secondary, and subordinate bus numbering and the rules governing these as used herein are contained in the PCI to PCI Bridge Architectural specification, revision 1.0, Apr. 5, 1994.
In particular, computer platforms with Windows 2000 and Windows XP Operating systems and system hardware implemented with, or expanded by a bridge resulting in, multi-level bridges are not able to rebalance PCI subsystems dynamically and do not properly assign memory and I/O resources needed by the subordinate buses. In other words, Windows 2000 and Windows do not properly support a bridge behind a bridge configuration.
Therefore, there is a need for a solution to allow for the proper configuration and resource allocation of bridges between computer bus's internal and external in desktop workstations, servers, and portable computers, that employ the Windows 2000 or Windows XP operating systems and variations thereof.